Microelectronic unit forming methods and materials

ABSTRACT

Electrically conductive elements such as terminals and leads are held on a support structure by a degradable connecting layer such as a adhesive degradable by heat or radiant energy. After connecting these elements to a microelectronic element such as a chip or wafer, the conductive elements are released from the support structure by degrading the connecting layer. The support structure desirably has a predictable, isotropic coefficient of thermal expansion and such coefficient of thermal expansion may be close to that of silicon to minimize the effect of the temperature changes. The conductive elements may be mounted on a plurality of individual tiles rather than on an unitary sheet covering an entire wafer to minimize dimensional changes when the dielectric is released from the support structure.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present application is a continuation of U.S. patentapplication Ser. No. 09/317,675, filed May 24, 1999, which is acontinuation-in-part of U.S. patent application Ser. No. 09/267,058,filed Mar. 12,1999, which in turn claims benefit of U.S. ProvisionalPatent Application 60/077,928, filed Mar. 13, 1998, the disclosures ofwhich are incorporated by reference herein. Application Ser. No.09/267,058 is also a continuation-in-part of U.S. patent applicationSer. No. 09/138,858 filed Aug. 24, 1998, which in turn is a divisionalof U.S. patent application Ser. No. 08/440,665 filed May 15, 1995, whichin turn is a divisional of U.S. patent application Ser. No. 08/271,768filed Jul. 7, 1994, now U.S. Pat. No. 5,518,964, the disclosures ofwhich are hereby incorporated by reference herein. Application Ser. No.09/268,058 is further a continuation-in-part of U.S. patent applicationSer. No. 09/140,589 filed Aug. 26, 1998, the disclosure of which is alsoincorporated by reference herein, which in turn claims benefit of U.S.Provisional Patent Application 60/056,965, filed Aug. 20, 1997, thebenefit of which is claimed herein and the disclosure of which is alsoincorporated by reference herein.

BACKGROUND OF THE INVENTION

[0002] The present invention relates to microelectronic packaging andmore particularly relates to methods of making connectors and packagedmicroelectronic components. In various microelectronic devices, it isdesirable to provide a connection between two components, which canaccommodate relative movement between the components. For example, wherea semiconductor chip is mounted to a circuit board, thermal expansionand contraction of the chip and circuit board can cause the contacts onthe chip to move relative to the corresponding electrically conductivefeatures of the circuit board. This can occur during service and canalso occur during manufacturing operations as, for example, duringsoldering operations on the circuit board.

[0003] As illustrated in certain preferred embodiments of U.S. Pat. No.5,518,964 (“the '964 patent”) movable interconnections between elementssuch as a semiconductor chip and another element can be provided byfirst connecting leads between the elements and then moving the elementsaway from one another so as to bend the leads. For example, a connectioncomponent may incorporate a dielectric body and leads extending along abottom surface of the dielectric body. The leads may have first or fixedends permanently attached to the dielectric element and connected toelectrically conductive features such as terminals, traces or the likeon the dielectric body. The leads may also have second ends releasablyattached to the dielectric body. The dielectric body, with the leadsthereon, may be juxtaposed with the chip and the second ends of theleads may be bonded to contacts on the chip. Following bonding, thedielectric body and chip are moved away from one another, therebybending the leads. During or after movement, a curable material such asa liquid composition is introduced between the elements. This is curedto form a compliant dielectric layer such as an elastomer or gelsurrounding the leads. The resulting packaged semiconductor chip hasterminals on the dielectric body connection component which areelectrically connected to the contacts on the chip but which can moverelative to the chip so as to compensate for thermal effects. Forexample, the packaged chip may be mounted to a circuit board bysolder-bonding the terminals to conductive features on the circuitboard. Relative movement between the circuit board and the chip due tothermal effects is taken up in the moveable interconnection provided bythe leads and the compliant layer.

[0004] Numerous variations of these processes and structures aredisclosed in the '964 patent. For example, the package-forming processcan be conducted on a wafer scale, so that the numerous semiconductorchips in a unitary wafer are connected to connection components in onesequence of operations. The resulting packaged wafer is then severed soas to provide individual units, each including one or more of the chipsand portions of the dielectric body associated therewith. Also, theleads may be formed on the chip or wafer rather than on the dielectricbody. In further embodiments, also disclosed in the '964 patent, aconnector for use in making connections between two othermicroelectronic elements is fabricated by a generally similar process.For example, in one embodiment a dielectric body having terminals andleads as discussed above is connected to terminal structures on atemporary sheet. The temporary sheet and dielectric body are moved awayfrom one another so as to bend the leads, and a liquid material isintroduced around the leads and cured so as to form a compliant layerbetween the temporary sheet and the dielectric body. The temporary sheetis then removed, leaving the tip ends of the terminal structuresprojecting from a surface of the compliant layer. Such a component maybe used, for example, by engaging it between two other components. Forexample, the terminal structures may be engaged with a semiconductorchip, whereas the terminals on the dielectric body may be engaged with acircuit panel or other microelectronic component. Thus, the broadinvention taught in the '964 patent offers numerous desirable ways ofmaking electrical interconnections and connectors.

[0005] Additional variations and improvements of the processes taught inthe '964 patent are disclosed in commonly assigned U.S. Pat. Nos.5,578,286; 5,830,782; and 5,688,716 and in copending, commonly assignedU.S. patent application Ser. No. 08/690,532, filed Jul. 31, 1996 and No.09/271,688, filed Mar. 18, 1999, the disclosures of which are herebyincorporated by reference herein.

SUMMARY OF THE INVENTION

[0006] The present application is directed to specific embodiments ofthe '964 patent process and certain embodiments thereof.

[0007] One aspect of the invention provides methods of making amicroelectronic assemblies. The methods in accordance with this aspectof the invention desirably include a the steps of providing leadsphysically connected to a bottom surface of a support, each said leadhaving a tip end and a terminal end and engaging the support with amicroelectronic element as, for example, a chip, a wafer or anassemblage of plural discrete chips, having contacts thereon so that thetip ends of the leads are aligned with the contacts of themicroelectronic element. The methods further include bonding the tipends of the leads to the contacts; and then after such bonding,selectively degrading the connection between the support and the leadsat and adjacent the tip ends thereof so as to free the tip ends from thesupport and leave the terminal ends secured to the support. Preferably,the methods include the further step of moving the support andmicroelectronic element through a predetermined displacement away fromone another after degrading the connection between the tip ends and thesupport so as to deform said leads towards a vertically-extensivedisposition. Optionally, the connection between the terminal ends of theleads and the support may be degraded after the moving step, so as tofree the support and allow removal of the support. A flowable materialmay be introduced around the leads during or after the movement step toform a dielectric layer surrounding said leads.

[0008] Where the material connecting the tip ends to the support isradiation-sensitive, the step of selectively degrading the connectionmay include selectively applying radiation through said support at andadjacent to the tip ends of the leads. Thus, in methods according tothis aspect of the invention, there is no need to fabricate precisemechanical features such as frangible connections to hold the leads inplace until they can be bonded to the microelectronic element. Instead,the tip ends of the leads are constrained reliably until such constraintis released by selective degradation of the connecting layer.

[0009] A related aspect of the invention provides methods of connectinga plurality of leads to one or more microelectronic elements. Methodsaccording to this aspect of the invention desirably include the steps ofproviding the leads physically connected to a support by a connectingmaterial so that said leads are maintained in position on the support atleast partially by the connecting material; juxtaposing the support withthe microelectronic element so that the leads are aligned with contactson the microelectronic element and bonding the leads to the contacts ofthe microelectronic element. After the bonding step, the connectionbetween the leads and the support is released by degrading theconnecting material. The step of degrading the connecting material mayinclude directing radiant energy through the support onto saidconnecting material. Preferably, the leads are flexible after they arereleased from the support. As further explained below, certain methodsaccording to this aspect of the invention provide for conversion ofconstrained, inflexible leads to a flexible state simply by releasingthe leads from the support, with or without a further step such asbending the leads.

[0010] A further aspect of the invention provides methods of making apackaged microelectronic component. Methods according to this aspect ofthe invention desirably include the steps of providing a supportincluding a structural layer transparent to radiation in a degradationwavelength band and electrically conductive elements secured to saidstructural layer by a connecting layer on a bottom surface of saidstructural layer. The conductive elements are connected to amicroelectronic component, and then the conductive elements are releasedfrom the structural layer by directing radiation in said degradationwavelength band through said structural layer to degrade the connectinglayer. The conductive elements or features provided on the support mayinclude leads as discussed above; individual conductive terminals; orconductive terminals incorporated in subassemblies also includingdielectric components. The step of connecting the conductive featurescarried by the support to a microelectronic component may includeproviding leads extending between said conductive features and themicroelectronic component.

[0011] The conductive features may be carried on a sacrificial layerhaving etching properties different from those of the conductivefeatures such that the sacrificial layer can be etched withoutdestroying the conductive features the sacrificial layer being connectedto said structural layer by said connecting layer. To provide suchdifferent etching properties, the sacrificial layer may be formed from amaterial different from the material constituting said conductivefeatures. Alternatively or additionally, the sacrificial layer may beformed from the same material as the conductive features but in athickness substantially less than the thickness of the conductivefeatures. Thus, degradation of the connecting layer frees thesacrificial layer from the structural layer. The method may furtherinclude etching the sacrificial layer to remove it without destroyingthe conductive features. The sacrificial layer can be used to conveyplating or etching currents during formation of the conductive features.

[0012] A related aspect of the invention provides a support or mandrelfor forming microelectronic elements incorporating a structural layertransparent to radiation in a degradation wavelength band; anelectrically conductive sacrificial layer thinner than the structurallayer; and a connecting layer securing said sacrificial layer to saidstructural layer, said connecting layer degradable by radiation in saiddegradation wavelength band.

[0013] Yet another aspect of the invention provides a structure forforming microelectronic assemblies. The structure includes a rigidsupport having a substantially uniform coefficient of thermal expansionand a plurality of electrically conductive elements connected to saidsupport by a connecting material, said support being transparent toradiation in a band of wavelengths effective to degrade said connectingmaterial. Such a structure can be used, for example, in the methodsdiscussed above. The electrically conductive elements on such structuremay include features such as leads and terminals. The element mayfurther include one or more sheetlike dielectric layers, the terminalsbeing exposed at a top face of said dielectric layer facing toward saidsupport.

[0014] A still further aspect of the invention provides a method ofmaking a plurality of packaged microelectronic components. The methodaccording to this aspect of the invention includes the steps ofproviding (i) a temporary support with a plurality of separatedielectric elements thereon, each such dielectric element havingelectrically conductive features thereon; (ii) a microelectronic unitincluding a plurality of microelectronic devices, and (iii) a pluralityof leads, the leads having first ends connected to conductive featureson the dielectric elements and having second ends attached to saidmicroelectronic devices. Once these elements have been provided, thetemporary support is at least partially removed so as to separate thedielectric elements from one another. Methods according to this aspectof the invention include the realization that, when a unitary dielectricsheet is connected to a relatively large microelectronic unit such as aunitary semiconductor wafer, the support may constrain the thermalexpansion of the sheet so as to suppress differential expansion andcontraction during to attachment process. However, when the support isremoved, the sheet tends to spring back to its unconstrained size. Thistendency is restrained by the wafer, leads and encapsulant. However,this tendency may impose internal stress in the assembly, which maydamage or distort the assembly. However, when smaller, individualdielectric sheets, also referred to herein as “tiles” are employed, theinternal stresses can be reduced substantially, typically by one or moreorders of magnitude. Moreover, because these tiles are present on thesupport during the steps used to connect the conductive features to themicroelectronic device, the support maintains the conductive features inthe correct spatial relationship for alignment with the contacts orother conductive features on the microelectronic element.

[0015] The connection between the tiles and a microelectronic elementsuch as a wafer may be made by means of leads carried on the bottomsurfaces of the tiles or on the top surface of the wafer. Mostpreferably, the step of providing the temporary support with saiddielectric elements includes fabricating said dielectric elements andconductive elements on the temporary support. Provided that the supporthas a predictable coefficient of thermal expansion, the conductivefeatures can be fabricated in precisely-controlled positions. In thisaspect of the invention as well, the temporary support may includefeatures such as a radiation-transmissive structural layer andradiation-degradable connecting layer to permit release of the tilesfrom the support. The support may also include an etchable sacrificiallayer.

[0016] A related aspect of the invention provides a component for makingpackaged microelectronic elements. The component includes a supporthaving a structural layer with a substantially uniform, isotropiccoefficient of thermal expansion, and a plurality of separate dielectricelements releasably attached to said support structure, said dielectricelements having conductive features thereon. Desirably, the support isformed from a material transparent to radiation of a predetermineddegradation wavelength, and the dielectric elements are secured to thestructural layer by a connecting material degradable by radiation insuch degradation wavelength band. Merely by way of example, thedegradation wavelength band may be in the ultraviolet range, the visiblerange, or the infrared range, although other wavelengths may be used.The transparent material desirably has a coefficient of thermalexpansion of about 6×10⁻⁶/° C. or less, so that the transparent materialis CTE-matched to silicon to within a reasonable tolerance.

[0017] A further aspect of the invention provides methods of makingmicroelectronic assemblies. Methods according to this aspect of theinvention desirably include the steps of providing a semiconductorelement such as a wafer including one or more semiconductor chips, saidsemiconductor element having contacts on a front surface and formingleads in place on the semiconductor element overlying the front surface,said leads having contact ends connected to the contacts and having tipends releasably connected to the semiconductor element; then juxtaposingsaid semiconductor element and leads with a further element such as asupport and/or dielectric element having pads thereon, and bonding saidtip ends of said leads to said pads. Most preferably, the pads arelarger than the contacts of the chip and desirably wider than the endsof the leads connected to the pads. As further discussed below, thisaspect of the present invention incorporates the realization that wherethe leads on the chips are aligned to pads wider than the ends of theleads, the process can operate satisfactorily even with a relativelylarge alignment tolerance. Typically, the contacts on the chip aredisposed at first center-to-center distances from one another and thepads are disposed at- second center-to-center distances larger than saidfirst center-to-center distances. As also discussed below, this providesroom for the pads to have relatively large diameter.

[0018] A related aspect of the invention provides an element for formingmicroelectronic assemblies. The element desirably includes a rigidsupport having a substantially uniform coefficient of thermal expansionand a plurality of electrically conductive structures defining padsfacing away from said support, the conductive structures beingreleasably connected to said support, the pads desirably being about 150μm to about 400 μm in diameter.

[0019] These and other objects, features and advantages of the inventionwill be more readily apparent from the detailed description of thepreferred embodiments set forth below, taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0020]FIG. 1 is a fragmentary, diagrammatic view depicting a portion ofa component utilized in one embodiment of the invention.

[0021]FIG. 2 is a diagrammatic, fragmentary sectional view taken on line2-2 in FIG. 1, depicting the component of FIG. 1 in conjunction with anadditional element during a process according to one embodiment of theinvention.

[0022]FIGS. 3 and 4 are views similar to FIG. 2 but depicting thecomponent of FIGS. 1 and 2 at later stages in the process.

[0023]FIGS. 5A, 5B, 6A and 6B are fragmentary, diagrammatic viewssimilar to FIG. 1 but depicting portions of components in accordancewith additional embodiments of the invention.

[0024]FIG. 7 is a fragmentary, diagrammatic sectional view depictingportions of a component in accordance with a further embodiment of theinvention.

[0025]FIGS. 8, 9 and 10 are views similar to FIG. 7 but depicting thecomponent in progressively later stages of a process according to afurther embodiment of the invention.

[0026]FIG. 11 is a fragmentary diagrammatic sectional view of depictinga component according to yet another embodiment of the invention.

[0027]FIG. 12 is a view similar to FIG. 11 depicting the component ofFIG. 11 in conjunction with a further element during a later stage ofthe process according to yet another embodiment of the invention.

[0028]FIG. 13 is a diagrammatic elevational view depicting componentsaccording to a further embodiment of the invention.

[0029]FIGS. 14 and 15 are views similar to FIG. 13 but depicting thecomponents of FIG. 13 during progressively later stages of the sameprocess.

[0030]FIG. 16 is a view similar to FIG. 13 but depicting components inaccordance with a further embodiment of the invention.

[0031]FIG. 17 is a fragmentary diagrammatic sectional view depicting acomponent according to yet another embodiment of the invention.

[0032]FIG. 18 is a fragmentary diagrammatic plan view depicting portionsof a component according to yet another embodiment of the invention.

[0033]FIG. 19 is a fragmentary perspective cutaway view of the componentshown in FIG. 18.

[0034]FIG. 20 is a diagrammatic sectional view on line 20-20 in FIG. 19,depicting the component of FIGS. 18-19 in conjunction with a furtherelement during a process according to the invention.

[0035]FIG. 21 is a view similar to FIG. 20 but depicting the componentat a later stage of the process.

[0036]FIG. 22 is a diagrammatic, fragmentary sectional view depictingcomponents according to a further embodiment of the invention in afurther process of the invention.

[0037]FIG. 23 is a fragmentary perspective view of a component shown inFIG. 22.

[0038]FIG. 24 is a sectional view of components according to a furtherembodiment of the invention.

[0039]FIG. 25 is a fragmentary top plan view of a wafer in accordancewith a further embodiment of the invention.

[0040]FIG. 26 is a fragmentary sectional view along line 26-26 in FIG.25, depicting the wafer in conjunction with a further element.

[0041] FIGS. 27-30 are fragmentary sectional views depicting portions ofa wafer during a lead-forming process.

[0042] FIGS. 31A-31J are fragmentary sectional view depicting portionsof a wafer during a further lead-forming process.

[0043]FIG. 32 is a diagrammatic view of a chip and a set of contacts.

[0044]FIGS. 33A and 33B are fragmentary, diagrammatic sectional viewsdepicting portions of leads and contacts during joining processes.

[0045]FIG. 33C is a diagrammatic perspective view depicting portions ofleads during a further joining process.

[0046]FIG. 34 is a fragmentary top plan view depicting a wafer inaccordance with yet another embodiment of the invention.

[0047]FIG. 35 is a sectional view taken along line 35-35 in FIG. 34,showing the wafer in conjunction with a further element during aprocess.

[0048] FIGS. 36A-36D are fragmentary sectional views of a wafer during alead-forming process in accordance with a further embodiment of theinvention.

[0049]FIG. 37 is a fragmentary view depicting a component in accordancewith a further embodiment of the invention, in conjunction withsemiconductor chips.

[0050]FIG. 38 is a sectional view taken along line 38-38 in FIG. 37 butdepicting the component and chip at a later stage of processing.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0051] A method in accordance with one embodiment of the presentinvention utilizes a support 30 including a structural layer 32 formedfrom a material having a substantially uniform, isotropic andpredictable coefficient of linear thermal expansion (“CTE”). In theprocess of FIG. 2, the support is to be engaged with a silicon elementsuch as a wafer, as further discussed below. Therefore, the coefficientthermal expansion of structural layer 32 preferably is close to thecoefficient of thermal expansion of silicon, i.e., the CTE of structurallayer 32 desirably is less than about 6×10⁻⁶/° C. and more preferablyabout 1.5 to about 6×10⁻⁶/° C., most preferably between 2×10⁻⁶/° C. and4×10⁻⁶/° C. Unless otherwise indicated, CTE values set forth in thisdisclosure are values at about room temperature (20° C.). Also, in theprocess of FIGS. 1-2, radiant energy is to be directed through thestructural layer 32 as further discussed below. Accordingly, structurallayer 32 is formed from a material that is transparent to suchradiation. Particularly preferred transparent structural materialsinclude glasses, quartz and silicon.

[0052] Support 30 further includes a connecting layer 34 formed from apolymeric material that is degradable by exposure to radiation in apredetermined degradation wavelength band. The thickness of connectinglayer 34 is greatly exaggerated in FIG. 2 for clarity of illustration.In practice, connecting layer 34 desirably is as thin as practicable.For example, connecting layer 34 may be formed from anultraviolet-degradable adhesive or other ultraviolet-degradable polymer.Some suitable ultraviolet-degradable adhesives are sold under thedesignations “Adwill D-570M”; “Adwill D-628”; “Adwill D-650” and “AdwillD-675” as UV-curable dicing tape by the LINTEC Corporation of Tokyo,Japan.

[0053] A set of conductive features including leads 36 is provided onthe bottom surface of the support, i.e., on the surface of the supportcovered by the connecting layer 34. Terms such as “bottom”; “top”;“upwardly”; and “downwardly” are used in this disclosure as referencingto the frame of reference of the components themselves, and need nothave any relation to the gravitational frame of reference. Each lead hasa first end 38, a second end 40 and an elongated portion 42 extendingbetween these ends. In the condition illustrated in FIGS. 1 and 2, theleads are generally planar and the elongated portion 42 of each lead iscurved in the plane of the lead. The leads are desirably formed frommetals such as one or more metals selected from the group consisting ofcopper, copper-bearing alloys, gold and gold-bearing alloys. Thedimensions of the leads will vary with the application. However, forcomponents to be connected to semiconductor chips, the leads typicallyare about 250-1000μm long from first end 38 to second end 40, about15-75 μm wide, and about 5-25 μm thick in the vertical directionperpendicular to the plane of connecting layer 34. Each lead also has amass of conductive bonding material 44 disposed on its second end. Thebonding material masses face away from support 30. Bonding material 44may be essentially any electrically conductive bonding material as, forexample, a solder; a eutectic bonding material; a diffusion bondingmaterial or an electrically conductive polymeric bonding material. Thebonding material 34 may also be an anisotropic conductive material suchas a polymer filled with electrically conductive particles. Desirably,conductive bumps (not shown) are deposited on chip contacts 50 forprotection of the chip contacts and the underlying semiconductorstructures from damage during bonding operations. For example, the bumpsmay include electrolessly deposited zincated nickel with an overcoatingof gold.

[0054] Leads 36 desirably are formed in place on the bottom surface ofthe support. For example, a layer of copper or suitable lead-formingmethod may be bonded to the bottom surface by connecting layer 34 andthen selectively etched using conventional masking and etchingtechniques to leave the leads in place on the bottom surface.Alternatively, the leads may be formed by an additive process as, forexample, by depositing a thin layer of a seed material by conventionalelectroless plating on the connecting layer and then selectivelyelectroplating the lead material onto the seed layer, followed byremoval of the masking material and the brief etch to remove the seedlayer in areas other than the areas covered by the leads. The conductivefeatures or leads 36 are disposed in a pattern corresponding to thepattern of contacts on a microelectronic unit to be used in the process.In the process of FIGS. 1-4, the microelectronic element is asemiconductor wafer 48 (FIG. 2) having a large number of contacts 50exposed at a top surface 52 of the wafer.

[0055] Support 30 with conductive features or leads 36 thereon isjuxtaposed with the microelectronic unit or wafer 48 so that the secondends 40 of the leads are aligned with the contacts 50 of themicroelectronic unit or wafer. Such alignment can be performed, forexample, using conventional robotic vision systems. The bonding material44 at the second ends of the leads is activated so as to bond the secondends of the leads to the contacts. For example, where the bondingmaterial is heat-activated bonding material such as a solder, eutecticbonding alloy or diffusion bonding alloy, the components are brought toan elevated temperature. The components may be forced against oneanother by a pair of heated platens (not shown), so that heat is appliedby conduction through the structural layer 32 of the support and throughthe wafer 48.

[0056] The structural layer 32 of support 30 greatly facilitates precisealignment of the lead ends and the contacts in the stages of theprocess. Because the CTE of the structural layer and hence the CTE ofsupport 30 as a whole is predictable and isotropic, any change inalignment can be predicted in advance and accounted for in the initialplacement of the leads. For example, if the CTE of the structural layeris slightly greater than the CTE of wafer 48, and if the lead-formingprocess is conducted at room temperature whereas the bonding step isconducted at elevated temperatures, the spacing between lead second ends40 used in the lead forming step may be slightly less than the nominal,room-temperature spacing between contacts 50 on the wafer. When bothparts are heated to the bonding temperature, the structural layer willexpand to a slightly greater degree than the wafer and hence the spacingbetween the leads second ends will be matched to the spacing between thecontacts 50. Desirably, the structural layer has a uniform CTE close tothat of silicon, and thus temperature changes during the process willintroduce only minimal changes in alignment between the lead second endsand the contacts on the wafer.

[0057] After the second ends of the leads have been bonded to thecontacts on the wafer, connecting layer 34 is degraded by applyingradiant energy selectively through structural layer 32 in regions 54aligned with the second ends of the leads and elongated portions 42 ofthe leads. The wavelength of the radiant energy is within thedegradation wavelength band of connecting layer 34. For example, wherethe bond layer 34 is degradable by ultraviolet radiation, the radiationapplied in regions 54 includes ultraviolet radiation. The radiation maybe applied selectively by use of an opaque mask 56 having openings 58aligned with the regions 54 where the radiant energy is to be applied.The radiant energy may be directed non-selectively onto the top surfaceof mask 56 and blocked by the mask at all locations other than theopenings 58. Alternatively, the radiant energy may be applied byselectively directing a beam of radiant energy such as a beam from alaser downwardly onto the top of the structural layer 32, so that thelaser beam impinges on the structural layer only in regions 54 whereradiant energy is desired.

[0058] As best appreciated with reference to FIG. 1, regions 54 may begenerally in the form of elongated strips extending transverse to thedirection of elongation of the leads. For example, a laser beam may bescanned across support 30 in a raster pattern having scanning linescorresponding to the individual strip-like regions 54. The registrationof the radiant energy pattern with the leads need not be particularlyprecise. Moreover, it is not necessary that the radiant energycompletely degrade the bond strength in the regions where it is applied.For example, if some portion of the connecting layer at the second endof each lead remains unaffected by the radiant energy, the process willstill operate properly, provided that the overall bond strength at thesecond end is sufficiently degraded that the connection between thesecond end 40 of the lead and structural layer 32 of support 30 isweaker than the bond between the second end of the lead and the contact50 of the wafer. As further discussed below, the second ends 40 andelongated portions 42 of the leads are peeled away from the supportstructure, starting at the second ends of the leads. Therefore, providedthat the radiant energy affects the bond at the second end sufficientlyfor the second end to be peeled away from the support structure, thepeeling process will begin at the second end and continue along thelength of the lead, even if some or all of the bonds between the supportstructure and the elongated portions 42 are unaffected by the radiantenergy. Also, if some portion of the connecting layer at the first endof each lead is affected by the radiant energy, the system will stilloperate properly provided that the remaining bond strength at the firstend of each lead is sufficient that the first end remains attached tothe support layer during the next step of the process. After theconnecting layer 34 has been selectively degraded at the second ends ofthe leads, support 30 and wafer 48 are moved away from one another in avertical direction V through a preselected distance. For example, thewafer and support may be moved away from one another by the controlledmovement of platens engaged with the top surface of support 30 and thebottom surface of wafer 48. During this movement, the support and wafermay also move in a horizontal direction H relative to one another.During this relative movement, the second ends 40 of the leads remainattached to the contacts 50 of the wafer and hence move downwardlyrelative to the support with the wafer. The first ends 38 of the leadsremain attached to support 30. Thus, the relative movement of thecomponents deforms the leads from their generally planar condition (FIG.2) to the vertically extensive disposition depicted in FIG. 3. During orafter such movement, a flowable composition adapted to form a dielectriclayer as, for example, a curable liquid composition arranged to form acompliant dielectric layer 60 such as a foam, a gel or an elastomer isintroduced between the support 30 and wafer 48. This material is curedto form the dielectric layer intimately surrounding the leads. Theprocess of moving the parts away from one another may be conducted asdiscussed in the aforementioned '964 patent. Also, the flowablecomposition may be introduced under a pressure greater than theprevailing atmospheric pressure surrounding the components, and thepressure of the flowable composition may help to impel the wafer andsupport away from one another. For example, to provide greater assuranceagainst formation of gas bubbles in the dielectric layer, the wafer, thesupport, and the space between these components may be maintained undera subatmospheric pressure and the flowable composition may be introducedunder atmospheric pressure or superatmospheric pressure.

[0059] After dielectric layer 60 has been cured, radiation in thedegradation wavelength band is applied to at least those areas of thesupport which were not treated in the prior selective application of theradiant energy, so as to degrade the remaining portions of connectinglayer 34 at the first ends of the leads. In this step, the radiantenergy may be applied either selectively at those portions of thesupport aligned with the first ends of the leads or non-selectively overthe entire support as depicted in FIG. 3. After degradation of theremaining portions of connecting layer 34, the structural layer 32 ofthe support is removed, leaving the first ends 36 of the leads asterminals exposed at a surface 62 of the dielectric layer 60 remote fromwafer 48, as depicted in FIG. 4. The resulting product can then besevered or “diced”, as by conventional wafer-sawing equipment, to formindividual units, each including one semiconductor chip with theassociated leads 36 and exposed terminals 38. Such a unit or packagedchip can be mounted to a circuit or other circuit panel with theterminal 38 bonded to the circuit panel. As described in greater detailin the '964 patent, relative movement between the chip and the circuitpanel caused, for example, by thermal expansion and/or warpage of thecomponents during operation and during manufacturing processes willaccommodated by flexure of leads 36. Thus, such relative movement willnot impose substantial stresses on the solder or other bonding materialused to secure terminals 36 to the circuit panel.

[0060] Other lead configurations, such as those illustrated in FIGS. 5A,5B, 6A, and 6B may be employed. The lead of FIG. 5A, which incorporatestwo elongated, curved main sections 42 provides a pair of connectionsextending in parallel between the first and second ends. Leads of thistype are discussed further in U.S. Pat. No. 5,859,472, the disclosure ofwhich is hereby incorporated by reference herein. Straight leads asshown in FIGS. 6A are also described in certain embodiments of theaforementioned '964 patent can be employed. Typically, where suchstraight leads are employed, the support structure 30 and wafer 48 moverelative to one another in a horizontal direction so that the second end44 of the lead moves towards the first end 38 in the horizontaldirection while the second end moves away from the first end in thevertical direction. This action is described in greater detail in theaforementioned '964 patent. Still other lead configurations which can beused in processes according to this aspect of the invention aredisclosed in co-pending, commonly assigned U.S. patent application Ser.No. 08/712,855, the disclosure of which is hereby incorporated byreference herein.

[0061] A process according to a further embodiment of the invention usesa support 130 with a structural layer 132 and the connecting layer 134similar to the corresponding elements discussed above with reference toFIGS. 1-4. Support 130 further has a sacrificial metal layer 135disposed on its bottom surface, i.e. on the surface of connecting layer134 so that the connecting layer holds the sacrificial layer on thesupport layer. Here again, the layer thicknesses are greatlyexaggerated. Typically, sacrificial layer 135 is a foil about 5 to about25 μm thick. Sacrificial layer 135 is formed from an electricallyconductive material different from the material used to form the leads.The material of the sacrificial layer desirably can be etched by anenchant which does not substantially attack the material of the leads.For example, where the leads are formed from gold or a gold-bearingalloy, the sacrificial layer may be formed from copper or acopper-bearing alloy where the leads are formed from copper or copperalloy, the sacrificial layer may be formed from aluminum or an aluminumalloy.

[0062] As illustrated in FIG. 7, the leads may be formed in a place byan additive plating process wherein a masking layer 137 such as aconventional photoresist is deposited on the surface of sacrificiallayer 135 leaving openings. The leads 136 are plated onto thesacrificial layer in such openings. Alternatively, a layer oflead-forming material may be provided on the surface of the sacrificiallayer and the leads may be formed by a subtractive etching process. Insuch a subtractive process, the masking material is applied over thelead-forming material in the areas where the leads are to be formed. Ineither case, the sacrificial layer 135 may be used to conduct plating oretching currents. The sacrificial layer thus simplifies fabrication ofthe leads. Again, a conductive bonding material 144 may be deposited atthe second ends of the leads.

[0063] In the next stage of the process, the masking material is removedand the bottom surface of the support, with the leads and sacrificiallayer thereon, is exposed to an enchant which attacks the sacrificiallayer but which does not substantially attack the leads. Areas of thesacrificial layer that are not covered by the leads 136 are removedrapidly. Also, in areas of the sacrificial layer covered by therelatively narrow elongated main portions 144 of the leads, thesacrificial layer is removed from between the lead and the connectinglayer 134. The first end 138 of each lead has a large diameter so thatit effectively shields a portion of the sacrificial layer. Although thesacrificial layer is attacked at the edges of the first end 138, theetching process is stopped before the sacrificial layer is completelyremoved at the first end. Thus, a connector 139 formed from thesacrificial layer material remains at the first end of each lead.Similarly, at the second end of 140 of each lead, a small connector orbutton 141 remains when the etching process is terminated. Buttons 141are substantially smaller than connectors 139. The buttons provide onlya weak connection between the second end of each lead and the connectinglayer 134; the strength of the connection is directly related to thesurface area of the connecting layer covered by the residual portions ofthe sacrificial layer in buttons 141. The surface areas covered bybuttons 141 are substantially smaller than the surface areas covered byconnectors 139. Thus, after this process, the second end 140 of eachlead is releasably connected to the connecting layer 134 whereas thefirst end 138 remains strongly attached to the connecting layer.

[0064] In the next stage of the process, the support structure 130, withleads thereon is juxtaposed with a wafer 148. The second ends 140 of theleads are aligned with the contacts 150 of the wafer and bonded theretoby means of the bonding material 144. The support structure and waferare then moved away from one another and a curable material is injectedto form a dielectric layer 160 in the same manner as discussed abovewith reference to FIG. 3. Buttons 141 break away from connecting layer134. In a variant of this process, the connecting layer can be degradedselectively at the second ends of the leads as discussed above. Aftercuring of the dielectric layer, connecting layer 134 is degradednon-selectively, over the entire area of support structure 130. Suchnon-selective degradation may be accomplished by exposure to radiantenergy as discussed above. Alternatively or additionally, the connectinglayer 134 may be degraded by exposure to heat or chemical agents.Suitable heat degradable materials for formation of a connecting layerare sold by the Nitto Denko Company of Japan. Where the bonding materialis heat degradable, the degradation temperature desirably is above thetemperatures attained in the stages prior to movement of the supportstructure and wafer away from one another. Stated another way, theconnecting layer material should remain effective at least for longenough to pull the lead first ends upwardly relative to the second ends140. Thus, connecting layer 134 desirably has a degradation temperatureabove the temperature used to activate the bonding material 144 at thesecond ends of the leads. Degradation of the connecting layer may occursimultaneously with or after curing of dielectric layer 160.Alternatively or additionally, connecting layer 134 may be chemicallydegraded by the material used to form dielectric layer 160. For example,the material of the connecting layer may be soluble in the curablecomposition used to form the dielectric layer. Also, the material usedto form the dielectric layer may carry a catalyst that initiatesdecomposition of the connecting layer.

[0065] Where the connecting layer is degraded by a phenomenon other thanan application of radiant energy through structural layer 132, thestructural layer may be opaque. Suitable opaque support materials havingthe desired coefficient of thermal expansion for use with a siliconwafer include molybdenum and Invar. The aforementioned preferredradiation-transmissive support layer materials, such as glasses,silicon, and quartz can also be used even if the radiation transmissiveproperties of these materials are not required.

[0066] In a further alternative, connecting layer 134 may be degraded byradiant energy such as infrared energy transmitted through wafer 148,either before or after introduction of the material used to form thedielectric layer 160. This approach is less preferred inasmuch asmetallic or other opaque structures within the wafer can blocktransmission of radiant energy. Also, the radiant energy must be appliedwithout overheating the internal structures of the wafer.

[0067] After degradation of connecting layer 134, structural layer 132is removed, leaving connectors 139 as exposed terminals at the surface162 of layer 160 remote from wafer 148. Here again, the wafer anddielectric layer 160 may be diced to form individual units. In a furtheralternative, connectors 139 may be removed by exposing surface 162 to anenchant adapted to dissolve the material of the sacrificial layer. Forexample, where connectors 139 are formed from aluminum left from analuminum sacrificial layer 135, an alkaline etch can be used to removethe connectors. This leaves the first ends 138 of the leads as terminalsexposed at surface 162 but slightly recessed beneath the surface. Theseterminals, however are still accessible for making further electricalcontact. For example, solder balls can be deposited on such recessedcontacts 138. Such solder balls can be engaged with a circuit panel.

[0068] In a method according to a further embodiment, a supportstructure 230 (FIG. 11) incorporates a structural layer 232 andconnecting layer 234 similar to the corresponding components of thesupport structure discussed above. A multi-layer structure 235 isdisposed on the bottom surface of the support, i.e., on the surface ofconnecting layer 234 facing away from structural layer 232. Themulti-layer structure includes several dielectric layers 237, 239, and241 as well as conductive elements such as through vias 201, traces 203extending in horizontal directions along or within the layers, and morecomplex conductive structures such as conjoined traces 205 and vias 207.

[0069] The conductive elements in the multi-layer structure 235 includeleads 236 having first ends 238 permanently connected to the dielectriclayers and second ends 240 releasably connected to the dielectriclayers. For example, the leads may be formed on the bottom dielectriclayer 241 and that layer may be etch so as to remove dielectric materialin the regions not covered by the leads and also remove dielectricmaterial from beneath the leads. Removal of material from the bottomdielectric layer leaves small polymeric connecting elements 241 at thesecond ends of the leads. These small connecting elements are breakable,and hence the second ends of the leads are releasably connected to theremainder of the structure 235. The first ends of the leads arepermanently attached to the structure; such as by vias or otherconductive features extending into the structure. Etching of polymericlayers may be performed, for example, using an oxidizing plasma.Processes for plasma etching to form releasable attachments between theleads and polymeric structures are discussed in greater detail incopending, commonly assigned U.S. patent application Ser. Nos.09/020,750 and 09/195,371, the disclosures of which are herebyincorporated by reference herein.

[0070] The dielectric layers can be formed in place on the surface ofthe support structure by processes such as electrophoretic deposition orspin-coating on the surface of the dielectric layer. Vias may be formedin such a deposited layers by conventional processes such as laserablation or etching. The metallic conductive structures can be providedusing additive processes such plating and/or subtractive processes suchas etching. Temporary metallic layers may be provided to convey platingor etching currents. Other conductive structures may be provided inmulti-layer structures 235, such as electrically conductive groundand/or power planes. Temporary connections may be provided for conveyingplating or etching currents by forming temporary conductive features(not shown) in areas of the structure will later be removed from thefinished product.

[0071] Alternatively, the multi-layer structure 235 may be foundseparately from the structural layer and laminated thereto using bondlayer 234 as laminating adhesive. Formation of the multi-layer structurein place on support 232 is preferred, however, because the supportcontrols the position of the various features during the formationprocess. Stated another way, when the features are formed in place onthe support, they can be positioned with great accuracy because theexpansion and contraction of the dielectric layers are controlled by thesupport during the process.

[0072] In a process according to a further embodiment of the invention,support 232 is juxtaposed with a wafer 248 or other microelectronicelement so as to align the second ends 240 of the leads with thecontacts 250 of the wafer. The second ends of the leads are bonded tothe contacts and the support structure is moved away from the wafer inthe manner described above. The connecting elements 241 peel away fromthe leads or break during this process. The dielectric layer 260 isformed by introduction of a flowable material and curing of suchmaterial as described above. After the support structure has been movedaway from the wafer, connecting layer 234 (FIG. 11) is degraded, as byapplication of radiant energy through support layer 232 or byapplication of heat so as to release the structural layer. Thestructural layer of the support is removed from the multi-layerstructure 235, leaving the assembly as illustrated in FIG. 12. Hereagain, the assembly can be diced to form individual units, eachincluding one or more chips and a portion of the multi-layer structure235 electrically connected thereto by the vertically extensive leads236.

[0073] Electrically conductive features such as vias 201 and 207 formterminals exposed to the top surface of the dielectric structure, i.e.,to the surface facing toward support layer 232. The terminals or vias201, 207 provided in the multi-layer dielectric structure can be used asterminals for mounting each unit to a circuit board or other component.As described in greater detail in the aforementioned '964 patent and asdiscussed above herein, the flexible, vertically extensive leads 236allow movement of the terminals 201, 207 relative to the contacts 250 onthe wafer or chip and hence provide compensation for differentialthermal expansion and similar effects during manufacture or service.

[0074] As depicted in FIG. 13, a support structure 330 may include aunitary structural layer 332 having horizontal dimensions (to the leftand the right as seen in FIG. 13) comparable to the correspondingdimensions of a wafer 348. Structural layer 332 may be similar to thestructural layers discussed above. The support further includes aconnecting layer 334 on the bottom surface of the structural layer. Aset of individual elements or tiles 335 is disposed on the bottomsurface of the support. Each tile desirably includes one or moredielectric layers as well as conductive features. For example, each tilemay be a multi-layer structure similar to that discussed above withreference to FIGS. 11 and 12 or else may be a simple, single-dielectriclayer structure. In the particular embodiment illustrated in FIG. 13,the conductive features include flexible leads 336 extending along thebottom surface of the dielectric element 337. The individual tiles arephysically connected to one another only by support by 330. Thus, thereare channels 339 extending between the tiles 335. However, the tiles,and particularly the conductive features such as leads 336 of the tiles,are disposed in precise relationship with one another so that thespacings between conductive features correspond to the spacings betweencontacts 350 of wafer 348. In a particularly preferred arrangement,tiles 337 are formed in place on the bottom surface of the support,i.e., on connecting layer 334. For example, all of the tiles may beformed as a unitary element including, for example, unitary dielectriclayers and/or unitary conductive layers or tracers extending among allof the tiles. These features can then be severed by laser-ablating theunitary layers and/or etching them to form channels 339. Other removalprocesses such as mechanical cutting, abrasion or water-jet machiningmay be used to form channels 339. As discussed above with reference toFIG. 11, conductive features can be formed using temporary conductiveelements in regions of the structure that are later removed. Suchtemporary conductive elements may be provided in the regions that areremoved to form channels 339.

[0075] Support structure 332, with tiles thereon 335 is engaged with awafer 348 in substantially the manner discussed above, so as to bond theends of leads 336 to contacts 350. The support structure is moved awayfrom the wafer so as to deform leads 336 into a vertically extensivedisposition (FIG. 14). Here again, a flowable material such as a liquidcomposition is introduced between the support structure and the waferand cured to form a dielectric layer, desirably a compliant dielectriclayer 360 such as a gel, foam or elastomer. During or after curing ofdielectric layer 360, connecting layer 334 is degraded, as byapplication of radiant energy, heat or chemical action so that supportstructural layer 332 can be removed. The resulting structure (FIG. 15)has the individual tiles attached to the wafer by the compliantdielectric layer 360 and by flexible, vertically extensive leads 336.The structure can be diced as by cutting along lines 353 between thetiles so as to provide individual units, each including one or morechips and a single tile or a few tiles.

[0076] The use of separate, individual tiles provides significantbenefits, particularly where process steps such as lead-bonding occur attemperatures significantly different from room temperature and/orsignificantly different from temperatures used in other steps of theprocess. The dielectric layers and conductive features typically havecoefficients of thermal expansion substantially greater than thecoefficient of thermal expansion of wafer 348. For example, a typicalpolyimide/copper structure has a CTE of about 17×10⁻⁶/° C., whereas thewafer typically has a CTE of about 3×10⁻⁶/° C. Where a unitarypolyimide/copper structure extends over an entire wafer of about 200-300mm diameter, the differential thermal expansion between thepolyimide/copper structure and the wafer through a temperaturedifference of about 200° C. may be on the order of 0.25-1 mm. Asmentioned above, the support structure, and particularly the rigidstructural layer 332 controls expansion and contraction of thepolyimide/copper structure during the bonding process. However, when thesupport structure is removed, the polyimide/copper structure tends tospring back to its normal, unconstrained size. Thus, the conductivefeatures on the polyimide/copper structure tend to move relative to thecontacts of the wafer of by 0.25 mm-1 mm or more.

[0077] While the flexible leads and compliant layer provided inaccordance with the preferred embodiments of this invention can providemore than enough compensation for the degree of differential expansionand contraction encountered in an assembly the size of a single chip ora few chips, they typically are not designed to permit 0.25 mm-1 mm ormore of relative movement. Therefore, internal stresses can be imposedwithin the assembly when an assembly incorporating a large, unitary,wafer sized polyamide/copper structure is released from the supportstructure. Typically, the compliant layer is placed in shear and some ofthe leads are placed in tension. The wafer is placed under stress whichtends to warp the wafer, and hence the entire assembly, out ofplanarity. By contrast, where the support structure bears individualtiles, tiles are free to move relative to one another when the supportstructure is removed. Thus, differential expansion and contractioneffects accumulate over only the extent of a single tile. The maximumrelative movement upon removal of the support corresponds to thedifferential expansion or contraction over the extent of a single tile,and not over the extent of a whole wafer. Typically, each tile is aboutthe size of a single chip or a few chips and has horizontal dimensionson the order of about 10-30 mm. Thus, the effects of differentialexpansion and contraction are dramatically reduced relative to the casewhere a unitary dielectric/conductive assembly is employed over theentire wafer.

[0078] A method according to yet another embodiment of the inventionuses a support structure 430 having an opaque structural layer 432 suchas a layer of solid molybdenum or other metal having CTE matched tosilicon, i.e., having a CTE less than about 6×10⁻⁶/° C. A set of tiles435 similar to the tiles discussed above with reference to FIGS. 13-15is provided on a bottom surface of support 430. The tiles are connectedto structural layer 432 by a heat-degradable bond layer 434. Also, leads436 are formed on the top surface of wafer 428 rather than on the tiles.Here again, each lead has a first end 438 and a second end 440. Thesecond ends of the leads are permanently connected to contacts 450 ofthe wafer. The first ends of the leads are movable relative to thewafer. In the bonding process, the first ends of the leads are alignedwith and bonded to conductive features such as contacts 451 on thetiles. Here again, the connected leads extend between the first elementor support structure 432 and tiles and the second element or wafer 428.Once again, the elements are moved away from one another so as to deformthe leads towards a vertically extensive disposition. A dielectric layeris formed around the leads as by introducing a curable composition. Thesupport structure 430 is then removed by degrading bond layer 434.

[0079] In yet another alternative, the support structure may include adegradable bond layer 534 on a structural layer 532 CTE matched to thewafer and may also include an etchable sacrificial layer 535 disposedbetween the bond layer and the tiles 537 (FIG. 17). After connectionwith the leads and forming the leads, bond layer 534 is released and theetchable sacrificial layer 535 is removed by etching. Sacrificial layer535 may be a thin foil as discussed above so as to minimize the timerequired for etching. Also, because the sacrificial layer issubstantially thinner than the structural layer, the structural layercontrols thermal expansion and contraction of the support as a whole.Desirably, the structural layer is at least 5 times, and more desirablyat least 10 times, as thick as the sacrificial layer. The sacrificiallayer may be subdivided into individual pieces, each associated with onetile, as by forming channels 541 in alignment with channels 539 betweenthe tiles. Channels 541 typically are formed after the sacrificial layerhas been used to convey plating or etching currents. This arrangementprovides the benefits associated with individual tiles as discussedabove. The same benefits can be obtained even where the tiles are notcompletely separated from one another. Thus, the channels 339 (FIGS. 13and 14) and/or channels 539 of FIG. 17 need not be continuous. Instead,such channels may be interrupted by connectors integral with the tilesextending between tiles. If these connectors are flexible enough toallow the tiles to move relative to one another, such relative movementof the tiles will still relieve stresses when the tiles are releasedfrom the support. Likewise, flexible connectors may extend betweenindividual pieces of the sacrificial layer, across channels 541. Theconnectors may be severed when the wafer is severed along cut lines 353(FIG. 15).

[0080] Similar benefits can be obtained even where the tiles are notcompletely separated from one another. Thus, the channels 339 (FIGS. 13and 14) may not be continuous but instead may be interrupted by bridgeelements integral with the tiles extending between tiles. If thesebridge elements are flexible enough to allow the tiles to move relativeto one another, such relative movement of the tiles will still relievestresses when the tiles are released from the support. The connectorsmay be severed when the wafer is diced.

[0081] As described in greater detail in the aforementioned U.S. patentapplication Ser. No. 09/140,589, leads can be made by forming gaps in alayer of material so as to form elongated lead regions partiallysurrounded by such gaps. For example, as seen in FIGS. 18 and 19, asheet including a polymeric layer 600 is provided with metallic strips602 on a bottom surface and strips 604 on a top surface overlying strips602. Gaps 606 extend around those portions of polymeric layer 600carrying strips 604 and 602, thus subdividing the polymeric sheet 600into a main region 608 and a set of lead regions 610. Each lead region610 forms a lead that can be bent or otherwise deformed independently ofthe other leads. Each such lead includes a first conductor 602 on thebottom surface and a second conductor 604 on the top surface. As bestseen in FIG. 19, the main portion 608 of the sheet carries a pair ofterminals associated with each such lead, including a first terminal 612connected to the first conductor 602 and a second terminal 614 connectedto the second conductor. These terminals are accessible at the topsurface of the sheet. Bonding material masses 616 and 618 are providedadjacent the second or tip end of each lead. Such a structure may beformed in place on the bottom surface of a support structureincorporating a structural layer 632 and connecting layer 634 similar tothe layers discussed above.

[0082] In a process according to an embodiment of the present invention,the sheet is juxtaposed with a wafer 648 and the bonding material massesare connected to contacts 650 on the wafer. Connecting layer 634 is thenselectively degraded in regions adjacent the tip ends 640 of the leadsand the support structure 630 is moved away from the wafer so as todeform the leads as depicted in FIG. 21. Once again, a curable materialis injected around the leads. The dual conductors 602 and 604 provide acircuit path having known, controlled impedance. As explained in greaterdetail in the aforementioned U.S. patent application Ser. No.09/140,589; and in co-pending, commonly assigned U.S. patent applicationSer. No. 08/715,571 filed Sep. 19, 1996 and Ser. No. 09/020,754 filedFeb. 9, 1998 and in PCT International Publication WO 97/11588, thedisclosures of which are hereby incorporated by reference herein, such acontrolled impedance signal path may incorporate a signal conductor anda ground plane or ground conductor extending generally parallel to oneanother, or else may include a set of two or more signal conductorsextending parallel to one another. As discussed in detail in theseapplications, a circuit 649 within the chip or wafer 648 may be arrangedto transmit oppositely-directed pulses on a set of adjacent contacts650. The conductors of a multi-conductor lead may be connected to thecontacts of such a set.

[0083] As also described in these applications, arrangementsincorporating more than two conductors on a lead may be employed as, forexample, a lead which incorporates three conductors such as a referenceconductor and two opposite signal conductors conveyingoppositely-directed pulses. As also described in these applications,multi-conductor signal paths and strip lines may extend along thedielectric layers. For example, the main region 608 of the dielectriclayer may be provided with one or more layers of signal conductors.These interconnections can provide controlled-impedance signal pathsbetween multiple components attached to the dielectric element. Also, asdescribed in International Publication WO 98/44564, the disclosure ofwhich is also incorporated by reference herein, such interconnectionsmay be used to provide controlled impedance signal paths between andamong contacts of a single semiconductor chip. All of these arrangementsmay be implemented in accordance with the present invention.

[0084] Multi-conductor leads may also be incorporated in methods andcomponents according to the other embodiments discussed above. Thus, theleads used in the embodiments discussed above with reference to FIGS.1-17 can be fabricated as multi-conductor leads with dielectric elementsin between the conductors. Conversely, a dielectric sheet of the typeused in the embodiment of FIGS. 18-21 can be fabricated as a pluralityof tiles as described above with reference to FIGS. 13-18.

[0085] In the embodiments discussed above, the leads are rendered moreflexible by bending them into a vertically extensive disposition, as bymoving the support and the wafer or chips away from one another.However, such a step may be omitted in certain cases. For example, asupport structure including a structural layer 732 and connecting layer734 (FIG. 22) carries a component incorporating a dielectric element anda set of leads 736. Each lead has a terminal at its fixed or first end738 on the dielectric layer and a second end 740 projecting from thedielectric layer. For example, the second ends of the leads may projectover apertures 741 in the dielectric layer or else may project beyondthe periphery of the dielectric layer. The leads have elongated mainportions 742. The main portions 742 are curved in the horizontaldirections, parallel to the plane of sheet 735. The particular zigzagshape illustrated in FIG. 23 is merely exemplary. The shapes shown inFIGS. 5A, 5B and 6B, and other shapes incorporating curved main portionscan be employed. These curved main portions allow freedom of movement ofthe second ends 740 relative to the first ends 738 in all horizontaldirections as, for example, in the directions towards and away from thefirst ends 738, as well as in vertical directions.

[0086] The component, including leads 736 is provided on the bottomsurface of the support structure. Here again, the component may befabricated in place on the bottom surface. The support structure holdsthe second ends of the leads in position, and prevents the leads fromflexing. The support structure is then engaged with a wafer or othermicroelectronic device 748 and the second ends of the leads 740 arebonded to the contacts 750 using bonding material carried on the secondends or on the contacts. As described in copending, commonly assignedU.S. patent application Ser. No. 09/233,586, filed Jan. 19, 1999, thedisclosure of which is hereby incorporated by reference herein, theleads used in this embodiment, and in the other embodiments discussedabove, may be provided with surfaces which are not wettable by theliquefied bonding materials bounding the second ends of the leads, sothat the liquefied bonding material does not tend to spread along theleads towards the first ends thereof during the bonding process. Afterthe second ends of the leads have been bonded to the contacts, theconnecting layer 734 is degraded as, for example, by application ofradiant energy or heat. The structural layer of support structure 730 isremoved. A compliant encapsulant (not shown) may be deposited over andaround the leads, leaving the first ends or terminals 738 exposed. Theleads, once freed from the support structure, allow movement of thecontacts on the chip relative to the first ends or terminals 738. Inmethods according to this aspect of the invention, the support structurestabilizes the lead second ends and allows accurate alignment of thelead second ends with the contacts on the wafer or microelectronicelement. Stated another way, in this process the leads are bonded to themicroelectronic component while a first condition in which leads areconstrained, and then the leads are brought to a second condition inwhich the leads are unconstrained, by releasing the lead tip ends fromthe support and, preferably, by removing the support.

[0087] In a variant of this approach, support 730 can include asacrificial layer and the process of freeing the leads from the supportmay include degrading the connecting layer so as to free the sacrificiallayer and then etching the sacrificial layer. According to a furthervariant, the structural layer of the support may be an aluminum or othermetal susceptible to etching. This approach however is less preferredinasmuch as it may expose the wafer to the etchant. In a further variantof this approach, dielectric layer 735 may incorporate a compliant layerto facilitate movement of the terminals 738 relative to themicroelectronic device in the finished assembly.

[0088] In a process according to a further variant of the invention, theelectrically conductive elements held on the support structure 830 (FIG.24) include terminals 838 disposed on a connecting layer 834. Amicroelectronic element in the form of a chip 848 is disposed on thesupport structure along with the electrically conductive terminals 838.The chip is disposed in a “face up” arrangement so that the contacts 850on the chip face away from the support structure. Wire bonds 836 areconnected between contacts 850 and terminals 838. Following wirebonding, a dielectric layer 860 is cast over the structure and thenconnecting layer 834 is degraded so that the structural layer 832 of thesupport structure can be removed. This leaves a complete, encapsulatedchip assembly including the dielectric mass with the chip and wire bondembedded therein, and with the contacts 838 exposed at the bottomsurface. The chip is also exposed at the bottom surface so as to promoteheat conduction from the chip. The finished assembly is generallysimilar to certain assemblies disclosed in International PatentPublication WO 97/39482, the disclosure of which is hereby incorporatedby reference herein. Other assemblies as shown in the '482 patentpublication may also be fabricated using similar techniques. However, inthe preferred assembly fabrication techniques according to this aspectof the present invention, it is not necessary to remove a sacrificiallayer by processes such as etching or laser ablation.

[0089] A wafer 948 partially depicted in FIG. 25 includes a large numberof semiconductor chips 949. Each chip has a large number of contacts 950disposed in one or more rows of adjacent contacts. The contacts withineach row lie at a relatively small center-to-center distances d,typically less than about 100 microns. Leads 936 are formed on the topsurface of the wafer. Only a few of the leads are depicted in FIG. 25.In practice, there may be tens or hundreds of contacts and acorresponding number of leads. Each lead 936 has contact end 940connected to a contact 950 on the chip and has a tip end 938 releasablysecured to the top surface of the chip or wafer. For example, the chipson the wafer may have a polyimide coating 901 overlying their topsurface 903, and the tip ends of the lead may be peelably connected tothis polyimide coating. The leads 936 typically are about 15-75micrometers wide and more typically about 25-50 micrometers. This widthdimension is comparable to the diameter of an individual contact 950.

[0090] The tip ends 938 of the leads are disposed in a “area array”,i.e., an array of regularly spaced tip ends 938 in a two dimensionalgrid pattern. This grid pattern is disposed in a central area 905 of thechip top surface, inside of the area bounded by the rows of contacts950. That is, the leads 936 “fan-in” or extend inwardly, toward thecenter of the chip front surface, from contacts 950 to tip ends 938. Asbest appreciated with reference to FIG. 25, the spacings D betweenadjacent lead tip ends 938 are larger than the spacings d betweenadjacent contacts and contact ends 940 of the leads.

[0091] The wafer 948 may be engaged with a further element having pads907 on a bottom surface. In the particular embodiment depicted in FIG.26, the further element includes a support 930 including a structurallayer 932 and connecting layer 934 as described above, having a set ofindividual tiles 935 held on the structural layer by the connectinglayer 934. The pads 907 are defined by metallic conductive elements onthe tiles. For example, pad 907 a is defined by a metallic via extendingentirely through the tile to a terminal 909 exposed at the top surfaceof the tile. Other pads such as pad 907 b are defined by metallicstructures connected to internal conductive elements such as traceswithin the tile.

[0092] Pads 907A are considerably larger in diameter than the contacts.Typically, the pads are about 150 to about 400 microns in diameter, andmore preferably about 250 to about 300 microns in diameter. These padstypically are about the same diameter as the terminals 909 exposed atthe top surface. These terminals in turn typically are sized to holdsolder balls. Pads 907 are disposed in an area array corresponding tothe array of lead tip ends 938. The layout of pads 907 is shown inbroken lines, superposed on the leads. As will be appreciated from FIG.25, the larger center-to-center distance between pads 907 allows for thegreater diameter of the pads.

[0093] The support 930, with the tiles 935 and pads 907 is aligned withthe wafer and engaged therewith in the manner discussed above. Eitherthe pads 907 or the lead tip ends 938 carry bonding material (notshown). The bonding material is activated to secure the lead tip ends tothe pads. After bonding, the support may be moved away from the wafer topeel a portion of each lead adjacent the tip end 938 away from the waferand thereby provide a more flexible interconnection between the tilesand the wafer. In the same manner as discussed above, a liquid materialadapted to form a dielectric layer may be injected between the supportand the wafer and cured, whereupon the structural layer 932 of thesupport is removed by degrading connecting layer 934.

[0094] In the embodiment of FIGS. 25 and 26, the leads are formed inplace on the top surface of the wafer. Therefore, the contact ends ofthe leads can be aligned precisely with the contacts 950 of each chip;such alignment can be as precise as the photographic patterningequipment used to fabricate the wafer. The tip ends 938 must be alignedwith the pads 907 during the bonding process by an operation involvingalignment of support structure 930 with the wafer. However, because thepads have substantially greater diameters than the contacts, thealignment tolerance in this operation is substantially increased byperforming the bonding between the tip ends of the leads and the pads907, rather than between the contact ends of the leads and the contacts.This relatively large tolerance is also enhanced by the fact that theleads have widths substantially smaller than the diameters of pads 907,and hence substantially smaller than the widths of the pads indirections transverse to the contact ends of the leads. All that isnecessary to form the correct bond is that the lead tip end engage thepad 907 at any point on the pad surface, so that the lead tip end canbond with the pad 907. A method of forming peelable leads on a surfaceof a wafer is illustrated diagrammatically in FIGS. 27-30. A wafer 948having contacts 950 thereon is provided with the polyimide layer 901.The polyimide layer is thick enough to provide a continuous,pinhole-free 3-15 μm. The polyimide layer is spun on using conventional“coater-developer” techniques. In these techniques, an uncured polyimideresin is coated onto the surface by applying the resin and spinning thewafer to distribute the resin. Apertures 920 are formed at each contact950 by conventional techniques during or after curing. A relativelythick aluminum layer 912 (FIG. 28), such as a layer about 0.5 to 1 μmthick, is deposited over the polyimide layer and over the contacts.Next, a metal such as copper or gold is selectively deposited on thealuminum layer 912 as by electroplating using masks (not shown) toprovide openings in the areas where the leads are desired. Using similarmasking techniques, a bonding material such as tin, solder or otherelectrically conductive bonding material 916 is deposited onto theregions that will form the tip ends 938 of the leads. Finally, afterremoving the masking layers, the wafer is exposed to an etchant thatattacks aluminum but which does not substantially attack the metal ofthe leads. The etchant removes the aluminum in the regions not coveredby the leads. However, a first connector 918 is left at the contact end940 of each lead, permanently connecting such end to the associatedcontact 950. A small button of aluminum 920 is left at the tip end 938of each lead, thereby releasably securing the tip end of the lead to thepolyimide layer 901. Depending upon the configuration of the leads,connectors 918 and buttons 920 may be formed without further masking.Thus, where the ends 940 and 938 are wider than the other portions ofthe leads, the aluminum will be removed from beneath the other portionsof the leads while some aluminum remains beneath the ends.Alternatively, where the leads are of uniform width, a masking materialmay be photographically patterned on the ends of the leads and left inplace during all or a portion of the etching procedure.

[0095] A further process for forming leads on a wafer or chip isdepicted in FIGS. 31A-31J. The process begins with a wafer 1148 having apassivation layer 1149 such as an oxide or nitride layer or a polymericlayer on a top surface and having contacts 1150 exposed throughapertures in the passivation layer. A photoimageable dielectric materialsuch as a photoimageable resist of the type commonly used insemiconductor processing operations is applied, imaged and developed soas to form a dielectric layer 1152 with apertures aligned with thecontacts 1150. A thin tie coat 1154 of nickel or otheradhesion-promoting material is sputtered onto the dielectric layer andcontacts, whereupon a further photoimageable resist 1156 is applied,imaged and developed so as to form openings 1157 in the regions whereleads are to be deposited. Each opening has an end aligned with acontact 1150 and an end remote from the contacts.

[0096] A lead-forming metal such as copper, gold or alloys orcombinations thereof is then plated onto the exposed surface of the tiecoat 1154 in openings 1157 so as to form leads 1160. A further resist1162 is applied over resist 1156, imaged and developed so as to leaveapertures 1164 at the ends of the leads remote from contacts 1150.Masses 1166 of a bonding material are deposited in these apertures.Resists 1162 and 1156 are then stripped away by conventional processes(FIG. 31H), leaving the tie coat 1154 exposed except in those areascovered by the leads. The tie coat is etched by a brief etching process,commonly referred to as microetching, which does not substantiallyaffect the leads or bonding material, as depicted in FIG. 31I. Thefirst-deposited dielectric layer or resist 1152 is then removed, asdepicted in FIG. 31J. The process leaves leads 1160 with first endsattached to the contacts 1150 of the wafer and with second or tip ends1170 remote from the contacts overlying the wafer surface but detachedtherefrom.

[0097] A wafer having leads 1160 thereon may be used in processes asdiscussed above, such as the process discussed above with reference toFIGS. 25-26. Here again, the lead tip ends 1170 can be engaged andbonded to contacts on another element such as a connection Desirably,the leads are deformed by moving the wafer and connection component awayfrom one another. As explained above, formation of the leads on thewafer provides significant advantages in that the leads can be preciselylocated on the wafer. Moreover, the tip ends can be engaged withcontacts that may be larger than the contacts on the wafer, whichsubstantially eases the requirements for precise alignment between thetip ends and the contacts. This effect is illustrated in FIG. 32. Theleads 1172 have fixed ends 1174 attached to contacts on a chip 1176. Thetip ends 1178 of the leads are engaged with contacts 1180 on a secondelement such as a connection component, the contacts being shown inbroken lines. The contacts may move over a range of positions that islarge relative to the tip ends of the leads and still make satisfactoryconnections to the tip ends. For example, the contact at position 1180 amay be in position 1180 a′ or 1180 a″, or any position intermediatebetween positions these positions and still make a satisfactoryconnection to lead tip end 1178.

[0098] In a variant of the process discussed above with reference toFIGS. 31A-31H, the process used to remove the dielectric layer 1152 frombeneath leads 1154 is a controllable process such as plasma etching, andthe process is controlled as discussed above with reference to FIG. 11to leave polymeric connecting elements at the tip ends of the leads,holding the leads in position until the tip ends have been bonded toanother element. In a further variant of this process, the polymericlayer 1152 is omitted, and the tie coat 1154 is deposited directly overthe passivation layer of the chip. The lead tip ends are detached fromthe chip by etching the passivation layer away after removing the otherresists. Processes discussed above with reference to forming leads onwafers may also be applied to form leads on individual semiconductorchips. Processes for forming leads on semiconductor elements may use thetechniques disclosed in commonly assigned U.S. Provisional PatentApplication 60/106,055, filed Oct. 28, 1998, the disclosure of which ishereby incorporated by reference herein.

[0099] As described in greater detail in the commonly assigned U.S.Provisional Patent Application entitled “Detachable Lead Structures andMethods” filed of even date herewith and naming David Light and JohnSmith as inventors (hereinafter, the “Light et al. Application”), thedisclosure of which is hereby incorporated by reference herein, the tipends of leads may be centered on the mating pads by surface tension in aliquid bonding material. As schematically shown in FIG. 33A, the leadmay initially be placed in a partially misaligned condition, depicted insolid lines, such that there is only a small region of overlap betweenthe tip end 1178 of the lead and the pad 1180. The lead tip end bears abonding material such as a solder or eutectic bonding alloy 1182 adaptedto form a liquid phase during the bonding operation, and adapted to wetthe surface of pad 1180. A portion of the liquefied bonding material1182 is disposed between the tip end of the lead and the pad, and wetsboth of these elements. The remainder of the bonding material is notdisposed between the tip end and the pad. Therefore, surface tensiontends to pull the liquefied bonding material into the relatively smallspace between the tip end and the pad. This action also moves the tipend of the lead, ultimately bringing the tip end of the lead to a fullyaligned condition depicted in broken lines in FIG. 3 at 1180′. Even inan embodiment where a liquefied bonding material is not used, largepads, where the lead has a relatively large degree of overlap with thepad, make electrical connections with the lead tip ends over a widerange of tip end positions.

[0100] As shown in FIG. 33B, the pads 1192 engaged with the tip ends ofleads 1190 may be elongated elements having directions of elongationtransverse to the direction of elongation of the lead 1190 at the tipend of the lead. This arrangement conserves space within the pad-bearingelement and on the pad-bearing surface, but still provides goodtolerance for misalignment between the lead tip and the pad. Providedthat the nominal position of the lead tip is selected so that the leadtip projects slightly beyond the pad, misalignment in the directionalong the lead simply shifts the pad relative to the lead. Misalignmentin the transverse direction shifts the lead along the long direction ofthe pad. The measures discussed with reference to FIGS. 33A and 33B canbe applied regardless of whether the pads are on a semiconductor devicesuch as a wafer or on a connection component or other element.

[0101] In a process according to a further variant, the pads on thebottom surface of an element 1193 are provided in the form of leadsections 1194 which extend transversely to the tip regions of leads 1195on chip or wafer 1196. At the inception of the process, the leadsections 1194 lie flat against the bottom surface of element 1193,whereas the leads 1195 lie flat on the top surface of chip 1196. The tipends of the leads 1195 are bonded to lead sections 1194 so as to formcomposite, generally L-shaped leads extending between the elements.After the bonding operation, element 1193 and the chip or wafer 1196 aremoved away from one another. During such movement, the composite,L-shaped leads are deformed to a vertically-extensive disposition, bybending leads 1195 away from the chip and by bending lead sections 1194away from element 1193. Stated another way, in this embodiment the padson the bottom surface of element 1193 are themselves elongated leads.This arrangement provides substantial tolerance for misalignment.misalignment in the X direction (the direction of elongation of leads1195) will simply shift the region where bonding occurs along leads1195, whereas misalignment in the Y-direction parallel to lead portions1194 will simply shift the bonding region along the lengths of leadportions or pads 1194. Moreover, lead portions 1194 of substantiallength can be accommodated on the bottom surface of element 1193 whilestill leaving substantial space for routing Y-direction traces 1197extending parallel to lead portions 1194 on the bottom surface.X-direction traces (not shown) can be placed on the top surface ofelement 1193 or within such element. The use of composite, generallyL-shaped leads is discussed in greater detail in copending, commonlyassigned U.S. patent application Ser. No. 09/281,688 filed Mar. 18, 1999the disclosure of which is hereby incorporated by reference herein.

[0102] A wafer 1048 (FIG. 34) includes a set of chips 1049, each havingcontacts 1050 disposed in a pair of rows adjacent the center of the chiptop surface. Leads 1036 include trace portions 1002 extending outwardlyfrom the contacts, and curved portions 1004 at the outer ends of thetrace portions defining the tip ends 1038 of the leads. In thisarrangement, the leads “fan-out” from the contacts 1050. Curved portions1004 of the leads are releasably connected to the chip top surface. Forexample, the leads may be fabricated as discussed above. Alternatively,the chip may bear a layer of polyimide or other dielectric and thedielectric may be etched from beneath the leads in a manner similar tothe etching of polyimide discussed above with reference to FIGS. 11-12.

[0103] The wafer of FIG. 34 is used in conjunction with a furtherelement including a set of electrically conductive pads 1007 (FIG. 35)carried on a connecting layer 1034, which in turn is carried on thebottom surface of a structural layer 1032 of a support 1030. Here again,the pads 1007 are disposed at greater center-to-center distances thanthe contacts, and the pads are of larger diameter than the contacts. Thepads are held in position relative to one another only by the support1030. After bonding the pads to the tip ends of the leads, the supportis moved away from the wafer so as to bend the curved portions 1004 ofthe leads, and a dielectric layer 1060 is formed by introducing acurable liquid into the space between the support and the wafer. Afterdegrading the connecting layer 1034, the support is removed, leaving thepads 1007 exposed as terminals on a surface of the dielectric layer1060.

[0104] Numerous variations and combinations of the features discussedabove may be utilized. For example, in the embodiments discussed above,a chip or wafer is connected to pre-formed conductive structures such asconductive structures on a connection component. However, as discussedin greater detail in commonly assigned International Publication WO98/28955, the disclosure of which is hereby incorporated by referenceherein, leads connected to a component such as a chip, wafer or othermicroelectronic element can be connected to a sheet of conductivematerial. The sheet may be moved away from the component to bend theleads, and a flowable material may be injected between the sheet andcomponent to form a dielectric layer. The sheet may then be etchedselectively to leave portions of the sheet as terminals connected to theleads. In a further variant, leads connected to a microelectronicelement may be attached directly to a circuit panel such as a circuitboard, rather than to a connection component.

[0105] Multiconductor leads may be formed on a chip or wafer. Forexample, as shown in FIGS. 36A-36D, a wafer 1300 having a passivationlayer 1302 has contacts 1304 aligned with openings in the passivationlayer. The contacts are arranged in sets, with the contacts of each suchset being disposed adjacent to one another. The contacts of each suchset may be connected to a single electronic device such as adifferential signal transmitter 1306 as discussed above with referenceto FIG. 21. A conductive sacrificial layer 1308 is applied over thepassivation layer (FIG. 36A) and patterned to form an opening alignedwith a first contact 1304 a of each set. A lead-forming metal is appliedin a pattern so as to form a first conductor 1310 overlying thesacrificial layer connected to the contact 1304 a of each set. Adielectric material such as a polyimide is applied and selectivelypatterned, as by photographically patterning the dielectric or etchingthe dielectric using a resist (not shown). The dielectric formsdielectric layers 1312 overlying the first conductor 1310 and firstcontact 1304 a of each set, but not covering the second contact 1304 bof each set. After selectively etching the sacrificial layer 1308 toform openings aligned with the second contact 1304 b of each set, afurther layer of lead-forming metal is applied and patterned so as toform second conductors 1314 overlying the first conductors but insulatedtherefrom by the dielectric layers 1312, each such second conductorbeing connected to the second contact 1304 b of a set. The wafer is thentreated with an etchant that attacks the sacrificial layer so as toremove the sacrificial layer. As discussed above, the etching processand feature design may be controlled so as to leave small anchors 1316at the tip end of each lead. The wafers according to this aspect of theinvention can be used with mating elements having contacts arranged insets. Thus, the conductors 1314 and 1310 of each lead can be bonded tocontacts disposed adjacent one another on a connection component, andthe connection component and wafer may be moved away from one another. Aflowable material may be injected to form a compliant dielectric layeras discussed above, and the wafer and connection component may besevered to form packaged chips. Alternatively, the wafer with themultilayer leads thereon may be severed to form individual chips havingsuch leads. The individual chips may be assembled to connectioncomponents to form packaged chips or, alternatively, may be assembled tocircuit panels such as circuit boards. In this case, the chip optionallymay be moved away from the circuit board, so as to deform the leads, anda flowable material may be injected around the leads. The same processesmay be used to make and process chips or wafers with multiconductorleads having more than two conductors per lead.

[0106] A component according to a further embodiment of the invention(FIGS. 37-38) includes a support structure 1400 including a transparentstructural layer 1402 and connecting layer 1404 susceptible todegradation by radiant energy. A set of tiles 1406 generally similar tothose discussed above with reference to FIGS. 13-17 is provided onconnecting layer. However, each tile has conductive features arranged ina “fanout” pattern. Thus, the tiles have leads 1408 with tip orreleasable ends 1410 disposed on the side of the tile facing away fromthe support structure 1400. The releasable ends of the leads aredisposed in a central area of the tile. The fixed end 1412 of each leadis connected to a conductive trace 1414 that extends outwardly towardsthe periphery of the tile to a contact 1416.

[0107] In use, individual semiconductor chips 1418 are aligned with thetiles and the contacts of the chips are bonded to the tip ends of theleads. This alignment and bonding step may be performed, for example, bygrasping each chip in a chuck attached to a robot and advancing theindividual chip onto the tile while applying heat and pressure throughthe chuck. During this process, the robot may register the position ofthe chip with the tiles by detecting fiducial marks on the supportstructure or tiles. Alternatively, a set of multiple chips disposed on afurther support at spacings corresponding to the spacings between tilesmay be aligned and bonded in a single operation.

[0108] After the chips have been bonded to the tiles, the chips and thetiles are moved away from one another by moving the chips away from thesupport structure 1400. For example, a unitary aluminum or otherthermally conductive heat spreader 1420 may be bonded to the rearsurfaces 1422 of all of the chips, and the heat spreader may be movedaway from the support structure so as to bend leads 1408 to thevertically-extensive condition illustrated in FIG. 38. A flowablematerial may be injected between the heat spreader and tiles and thencured as discussed above to form a dielectric layer such as a compliantlayer surrounding the leads. Desirably, the flowable material isintroduced under pressure so that the flowable material provides atleast some of the force necessary to cause such movement. The connectinglayer 1404 then may be degraded so as to release the tiles from thestructural layer 1402, and the heat spreader may be severed to formindividual units, each including a tile, a chip and a portion of theheat spreader.

[0109] In a variant of this procedure, individual heat spreaders mountedon a common support by a degradable connecting layer such as aUV-degradable layer may be used in place of a unitary support. Theindividual heat spreaders are separated from the common support afterthe chips are moved. In yet another variant, the rear surfaces of thechips may be bonded directly to a support by a degradable connectinglayer before moving the chips, and then freed from the support. The sameprocess may be applied using chips bearing leads as discussed above, inconjunction with tiles having traces thereon to form the fan-outpattern. In further variants, the pattern of conductive elements on thetiles forms a “fan-in/fan-out” pattern, wherein some of the externalconnecting terminals 1416 on the tile are disposed in the central areaof the tile covered by the chip, whereas other terminals are disposed inthe periphery of the tile, outside of the area covered by the chip.

[0110] As further described in the Light et al. Application filed ofeven date herewith, and in the aforementioned U.S. patent applicationSer. No. 09/267,058, connections between leads and a support may bedegraded by thermal processes such as by application of heat to degradea heat-degradable adhesive bond or by heating and/or cooling an assemblyhaving a metallic feature weakly adhering to a polymeric layer. Also,the degradation of the bond between a conductive feature such as a leadtip end may occur during the same process step or steps which forms abond between the conductive feature and a mating feature on an opposingelement.

[0111] As these and other variations and combinations of the featuresdiscussed above can be utilized without departing from the presentinvention as defined by the claims, the foregoing description of thepreferred embodiments should be taken by way of illustration rather thanby way of limitation of the claimed invention.

What is claimed is:
 1. A method of making a microelectronic assemblycomprising: (a) providing leads physically connected to a bottom surfaceof a support, each said lead having a tip end and a terminal end; (b)engaging said support with a microelectronic element having contactsthereon so that the tip ends of the leads are aligned with the contactsof the microelectronic element, and bonding the tip ends of the leads tothe contacts; (c) during or after said bonding, selectively degradingthe connection between the support and the leads at and adjacent the tipends thereof so as to free the tip ends from the support and leave theterminal ends secured to the support.